As the demand for cheaper, faster, lower power consuming microprocessors increases, so must the device packing density of the integrated circuit (IC). Very Large Scale Integration (VLSI) techniques have continually evolved to meet the increasing demand. The ability to place more IC devices on a semiconductor chip allows more complex and sophisticated functionality to be incorporated into the chip. Therefore, as a result of reducing the dimensions of an IC, products which use such IC's, such as, for example, home computers, will be able to operate faster and with greater functionality than ever before.
Minimizing transistor dimensions involves, among other things, minimizing the width which a photolithographic technology can resolve. Resolution of an image onto a photo-sensitive film is frustrated by even subtle variations in the film's topography, causing the image to shift in and out of focus across the surface of the film. Therefore, it is extremely important that the surface of the photo-sensitive film be as flat, or planar, as possible to avoid problems associated with optical imaging.
In a typical IC device manufacturing process, thick dielectric layers are formed over component features on a semiconductor substrate to insulate these components from electrical interconnects which are subsequently formed over the surface of the dielectric layer. For the dielectric layer to reliably insulate the underlying components of the semiconductor substrate, the aspect ratios of gaps in the underlying substrate must be kept low enough to prevent the formation of, for example, voids or other problems associated with step coverage.
Maximizing the speed at which an IC device operates not only requires the minimization of device dimensions but also the consideration of other electrical characteristics of the device. For example, one way to increase the speed at which a transistor operates is to reduce the resistance of the transistor gate electrode near the electrode/gate oxide interface. For IC technologies in which polycrystalline silicon (polysilicon) is the material used as the gate electrode of a transistor, minimizing the resistance of the polysilicon near the gate oxide interface involves maximizing the dopant concentration of the polysilicon in this region.
FIG. 1 shows a magnified cross-section of a polysilicon film 11 formed on substrate 10. Polysilicon film 11 is formed by depositing silicon onto the surface of substrate 10 in a low pressure chemical vapor deposition (LPCVD) chamber at a temperature of approximately 600.degree. C. using silane (SiH.sub.4) chemistry. Note the pronounced surface roughness on polysilicon film 11. The surface roughness of polysilicon film 11 is a result of the large-grained columnar crystal structures within the film. This pronounced surface roughness makes it difficult to obtain good patterning profiles due to the significant variation in inter-granular thickness of photoresist formed on the surface of the polysilicon film and the nonuniform reflectivity which occurs during the photolithographic patterning process. This results in poor edge definition for sub-half micron polysilicon lines. Therefore, the polysilicon film of FIG. 1 is not suitable for forming very narrow polysilicon lines such as those used to form polysilicon transistor gate electrodes because the rough surface topography of the polysilicon film frustrates the photolithographic process.
In addition to the difficulties in defining line widths using the polysilicon film shown in FIG. 1, this polysilicon film is prone to severe implant channeling. Implant channeling occurs in a polysilicon film when implanted dopant species enters the film either along a grain boundary or through a silicon crystal channel. The dopant species is projected straight through the polysilicon film and becomes imbedded into the underlying substrate. For applications in which the polysilicon film of FIG. 1 is implemented as the gate electrode as a transistor, this underlying substrate is an ultra thin, highly delicate gate oxide film. Dopant species, which channel through the polysilicon film and become embedded into the gate oxide film have the effect of degrading the quality of the gate oxide film, thereby reducing the reliability and performance of the transistor.
FIG. 2 shows a magnified cross-section of another polysilicon film 21 formed on substrate 20. Polysilicon film 21 is formed by a process in which silicon is deposited on the surface of a substrate in a LPCVD chamber at a temperature of approximately 550.degree. C. By depositing silicon at this lower temperature, an amorphous silicon film is created because crystal grains cannot develop at this low temperature. This amorphous silicon film is subsequently recrystallized by exposing the material to a temperature in excess of 600.degree. C. The result is the polycrystalline structure shown in FIG. 2 wherein large crystal grains are formed.
While the polysilicon film 21 of FIG. 2 overcomes the problems associated with surface roughness described above, polysilicon film 21 is highly prone to implant channeling. As discussed above, implant channeling degrades the performance and reliability of transistors. In addition, polysilicon film 21 suffers from poly-depletion effects.
In a typical transistor manufacturing process, dopants are introduced into a polysilicon film to improve the conductivity, reduce the resistance, and modulate the depletion layer of the gate electrode, thereby improving the speed of the transistor. These dopants diffuse throughout the polysilicon film primarily along the grain boundaries. Consequently, the higher the grain boundary density of a film, the better the diffusion of dopants through the film. As shown in FIG. 2, the large grain size of polysilicon film 21 reduces the grain boundary density of the film, thereby reducing the diffusion of dopant material through the film. As a result, a poly-depletion effect occurs wherein the poor conductivity and high resistance of the polysilicon film nearest the gate oxide boundary hinders the performance of the transistor. In addition, because the polysilicon film 21 is deposited at a low temperature, the deposition rate is similarly low, resulting in slow throughput times.
FIG. 3a is a cross-section of insulated transistors formed on a semiconductor substrate after the contact etch has been performed. Polysilicon gate electrodes 34 and 35 are formed over gate oxide films 33 on silicon substrate 30. Source/drain regions 32 are formed in the silicon substrate and silicide regions 31 and 37 are formed to reduce the resistance of the silicon. Dielectric layer 36 is deposited over the surface of the substrate and contact regions 38 and 39 are subsequently etched through dielectric film 36 to contact polysilicon gate electrode 34 and source/drain region 32, respectively.
Note that gate electrodes 34 and 35 have been made very thick. This has been done to minimize the likelihood that an implanted dopant will channel through the polysilicon film and implant itself into gate oxide 33. As a result of the large thickness of gate electrodes 34 and 35, the aspect ratio between these features is high, resulting in problems associated with adequately filling the region between the electrodes with dielectric material 36. In addition, the resulting high aspect ratio of contact opening 39 frustrates contact filling by a subsequently deposited metal plug.
In a typical etch process, the etch selectivity of dielectric layer 36 to polysilicon gate electrode 34 is not infinite. In practice, the etch chemistry used to etch contact openings 38 and 39 will also etch gate electrode 34 at a slower rate. Because the distance between the surface of gate electrode 34 and the surface of silicon substrate 30 is great, it takes a long time to fully etch dielectric 36 from region 39 after the silicide cap 37 of polysilicon gate electrode 34 is reached within region 38. During this time, the etch chemistry eats through silicide 37 and into the underlying polysilicon film of gate electrode 34. As a result, the contact resistance between a metal plug subsequently deposited into region 38 and gate electrode 34 is significantly increased because the low resistance silicide cap 37 has been entirely eaten away. This results in poor device performance.
FIG. 3b is a top-down view of FIG. 3a showing the poor edge definition of silicon gate electrodes 34 and 35 resulting from the rough surfaces of the polysilicon film of FIG. 1. Note that given the poor edge definition shown in FIG. 3b, precise characterization of the resulting transistors is made nearly impossible, and there is a large variation in transistor channel length, resulting in variations of speed of the transistor. In addition, the punch-through performance of the resulting transistors is significantly degraded.
What is desired is a polysilicon film which exhibits improved edge definition while still providing good dopant diffusion through the film. In addition, by reducing the channeling effects associated with implanting such a film, the performance and scalability of devices formed using the film can be significantly improved.